1. Field of the Invention
The present invention relates to a method and a device for timing random reading of a memory device.
2. Discussion of the Related Art
As is known, random reading of the data stored in a memory device involves execution of a succession of operations, each of which starts at the instant in which the previous one terminates.
The operations making up reading have a duration that varies according to the operating temperature and the supply voltage of the memory device, and, in particular, the duration of each operation decreases as the supply voltage increases and as the operating temperature of the memory device decreases.
The most widespread method for reading data stored in a memory device basically envisages comparison of a quantity correlated to the current flowing in the memory cell in which the datum to be read is stored with a similar quantity correlated to the current flowing in a reference memory cell, in which a known datum is stored.
In particular, to carry out reading of a memory cell, the gate terminal of the memory cell is supplied with a read voltage comprised between the threshold voltage of an erased memory cell and the threshold voltage of a written memory cell, in such a way that, if the memory cell is written, the read voltage is lower than its threshold voltage and, therefore, no current flows in the memory cell, whereas, if the memory cell is erased, the read voltage is greater than its threshold voltage and, consequently, there is current flowing in the memory cell.
Reading of a memory cell is carried out, as has been said above, by means of a reading circuit of the type described, for example, in the European patent application EP-A-0814480 filed on Jun. 18, 1996, in the name of the present applicant, the circuit diagram of which is represented, for reasons of convenience, in FIG. 1 and which is incorporated herein by reference.
According to what is illustrated in FIG. 1, the read circuit, designated as a whole by 1, basically includes an array branch 2 connected, via an array bitline 3, to an array memory cell 4, the contents of which is to be read; a reference branch 5 connected, via a reference bitline 6, to a reference memory cell 7, the contents of which is known; a current/voltage converter stage 8 basically made up of a current mirror connected to the array and reference branches 2, 5 for converting the currents flowing in the array memory cell 4 and in the reference memory cell 7 in respective electrical potentials; and a comparator stage 9 basically made up of a differential amplifier designed to compare said electrical potentials with one another in order to output a logic output signal OUT indicating the binary information “0” or “1” stored in the array memory cell 4.
Reading of a datum from the memory device typically entails simultaneous reading of a very high number of memory cells, and, consequently, during reading of a datum, there is normally a high current absorption from the supply, which generates sharp and sudden drops in the supply voltage that constitute in effect a noise superimposed on the nominal supply voltage.
Said sharp variations in the supply voltage, commonly referred to as “ripple”, adversely affect proper operation of the differential amplifier of the comparator stage 9, in so far as they cause instability of the output signal OUT generated by the latter and, consequently, indeterminacy and unreliability of the binary information read from the array memory cell 4.
The supply noise rejection of the read circuit, i.e., its insensitivity to the supply noise, deteriorates as the supply voltage increases but, above all, as the read time decreases, so that an improvement of the supply noise rejection could be obtained only at the expense of a significant increase in the time during which sensing of the stored datum is carried out by the differential amplifier of the comparator stage 9 and, consequently, at the expense of a significant increase in access time.
For this reason, in the memory devices in which each of the operations making up reading starts at the instant in which the previous operation terminates, it is not possible to reduce significantly the supply noise rejection of the read circuit.
Apart from this drawback, the memory devices in which each of the operations making up reading starts at the instant in which the previous operation terminates suffer from a further drawback linked to the data access time, which represents one of the most important parameters in evaluating the competitiveness of a memory device.
As is known, in fact, the data access time of a memory device can be defined as the time interval which elapses, in the worst operating conditions of the memory device, between the instant in time in which there occurs a variation of the addresses on the inputs of the memory device due to a request for reading a new datum and the instant in time in which the required datum is stably present on the outputs of the memory device and can therefore be read.
By way of example, FIG. 2 is a schematic illustration of the three parts which can be considered as making up the data access time. In particular, the access time is made up of: a first part, designated by the letter A, the time duration of which is equal to the time elapsing between the instant in time in which there occurs the variation of the addresses on the inputs of the memory device due to request for reading a new datum and the instant in time in which the read operations effectively start; a second part, designated by the letter B, the duration of which is equal to the time necessary for the read circuit to carry out reading proper of the datum from the memory cell, i.e., to carry out the so-called “sensing” of the datum; and a third part, designated by the letter C, the duration of which is equal to the time elapsing between the instant in time in which the read circuit supplies the datum read and the instant in time in which the datum read is stably available on the outputs of the memory device and can thus be read.
Since the data access time is defined in the worst conditions of operation of the memory device in terms of operating temperature and supply voltage, when the memory device operates in more favourable conditions, the datum required is supplied on the outputs of the memory device in a time that is shorter than the access time from when variation of the addresses has occurred.
In many applications, however, said advance is frequently cancelled out by the fact that the end user of the memory device carries out reading of the data only after a time interval has elapsed equal to the access time from when variation of the addresses on the inputs of the memory device has occurred.